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GAL20V8 high performance e 2 cmos pld generic array logic 1 228 nc i/clk i i i i i i i nc nc nc gnd i i i/oe i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q vcc i/o/q i i 4 5 7 9 11 12 14 16 18 19 21 23 25 26 plcc 1 12 13 24 i/clk i i i i i i i i i i gnd vcc i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i/oe 6 18 GAL20V8 top view gal 20v8 dip clk i i i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i/o/q i i i i i i i i i i i/oe i/clk oe 8 8 8 8 8 8 8 8 olmc olmc olmc olmc olmc olmc olmc imux imux programmable and-array (64 x 40) olmc copyright ?2000 lattice semiconductor corp. all brand or product names are trademarks or registered trademarks of their respec tive holders. the specifications and information herein are subject to change without notice. lattice semiconductor corp., 5555 northeast moore ct., hillsboro, oregon 97124, u.s.a. august 2000 tel. (503) 268-8000; 1-800-lattice; fax (503) 268-8556; http://www.latticesemi.com 20v8_04 features high performance e 2 cmos technology 5 ns maximum propagation delay fmax = 166 mhz 4 ns maximum from clock input to data output ultramos advanced cmos technology 50% to 75% reduction in power from bipolar 75ma typ icc on low power device 45ma typ icc on quarter power device active pull-ups on all pins e 2 cell technology reconfigurable logic reprogrammable cells 100% tested/100% yields high speed electrical erasure (<100ms) 20 year data retention eight output logic macrocells maximum flexibility for complex logic designs programmable output polarity also emulates 24-pin pal devices with full function/ fuse map/parametric compatibility preload and power-on reset of all registers 100% functional testability applications include: dma control state machine control high speed graphics processing standard logic speed upgrade electronic signature for identification description the GAL20V8c, at 5ns maximum propagation delay time, com- bines a high performance cmos process with electrically eras- able (e 2 ) floating gate technology to provide the highest speed performance available in the pld market. high speed erase times (<100ms) allow the devices to be reprogrammed quickly and ef- ficiently. the generic architecture provides maximum design flexibility by allowing the output logic macrocell (olmc) to be configured by the user. an important subset of the many architecture configura- tions possible with the GAL20V8 are the pal architectures listed in the table of the macrocell description section. GAL20V8 devices are capable of emulating any of these pal architectures with full function/fuse map/parametric compatibility. unique test circuitry and reprogrammable cells allow complete ac, dc, and functional testing during manufacture. as a result, lattice semiconductor delivers 100% field programmability and function- ality of all gal products. in addition, 100 erase/write cycles and data retention in excess of 20 years are specified. functional block diagram pin configuration
2 specifications GAL20V8 ) s n ( d p t) s n ( u s t) s n ( o c t) a m ( c c i# g n i r e d r oe g a k c a p 0 10 17 0 3 1 8 v 0 2 l a gci j l 0 1 - c c l p d a e l - 8 2 0 3 1i p l 0 1 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 0 3 1i j l 0 1 - b 8 v 0 2 l a gc c l p d a e l - 8 2 5 12 10 10 3 1i p l 5 1 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 0 3 1i j l 5 1 - b 8 v 0 2 l a gc c l p d a e l - 8 2 0 23 11 15 6i p q 0 2 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 6i j q 0 2 - b 8 v 0 2 l a gc c l p d a e l - 8 2 5 25 12 15 6i p q 5 2 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 6i j q 5 2 - b 8 v 0 2 l a gc c l p d a e l - 8 2 0 3 1i p l 5 2 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 0 3 1i j l 5 2 - b 8 v 0 2 l a gc c l p d a e l - 8 2 industrial grade specifications blank = commercial i = industrial grade package power l = low power q = quarter power speed (ns) xxxxxxxx xx x x x device name _ p = plastic dip j = plcc GAL20V8c GAL20V8b ) s n ( d p t) s n ( u s t) s n ( o c t) a m ( c c i# g n i r e d r oe g a k c a p 534 5 1 1j l 5 - c 8 v 0 2 l a gc c l p d a e l - 8 2 5 . 775 5 1 1 8 v 0 2 l a gcj l 7 - c c l p d a e l - 8 2 5 1 1p l 7 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 1 1j l 7 - b 8 v 0 2 l a gc c l p d a e l - 8 2 0 10 17 5 1 1 8 v 0 2 l a gcj l 0 1 - c c l p d a e l - 8 2 5 1 1p l 0 1 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 1 1j l 0 1 - b 8 v 0 2 l a gc c l p d a e l - 8 2 5 12 10 15 5p q 5 1 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 5j q 5 1 - b 8 v 0 2 l a gc c l p d a e l - 8 2 0 9p l 5 1 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 0 9j l 5 1 - b 8 v 0 2 l a gc c l p d a e l - 8 2 5 25 12 15 5p q 5 2 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 5 5j q 5 2 - b 8 v 0 2 l a gc c l p d a e l - 8 2 0 9p l 5 2 - b 8 v 0 2 l a gp i d c i t s a l p n i p - 4 2 0 9j l 5 2 - b 8 v 0 2 l a gc c l p d a e l - 8 2 GAL20V8 ordering information commercial grade specifications part number description
specifications GAL20V8 3 the following discussion pertains to configuring the output logic macrocell. it should be noted that actual implementation is accom- plished by development software/hardware and is completely trans- parent to the user. there are three global olmc configuration modes possible: simple , complex , and registered . details of each of these modes is illustrated in the following pages. two global bits, syn and ac0, control the mode configuration for all macrocells. the xor bit of each macrocell controls the polarity of the output in any of the three modes, while the ac1 bit of each of the macrocells controls the in- put/output configuration. these two global and 16 individual archi- tecture bits define all possible configurations in a GAL20V8 . the information given on these architecture bits is only to give a bet- ter understanding of the device. compiler software will transpar- ently set these architecture bits from the pin definitions, so the user should not need to directly manipulate these architecture bits. the following is a list of the pal architectures that the GAL20V8 can emulate. it also shows the olmc mode under which the devices emulate the pal architecture. software compilers support the three different global olmc modes as different device types. these device types are listed in the table below. most compilers have the ability to automatically select the device type, generally based on the register usage and output enable (oe) usage. register usage on the device forces the soft- ware to choose the registered mode. all combinatorial outputs with oe controlled by the product term will force the software to choose the complex mode. the software will choose the simple mode only when all outputs are dedicated combinatorial without oe control. the different device types listed in the table can be used to override the automatic device selection by the software. for further details, refer to the compiler software manuals. when using compiler software to configure the device, the user must pay special attention to the following restrictions in each mode. in registered mode pin 1 and pin 13 (dip pinout) are permanently configured as clock and output enable, respectively. these pins cannot be configured as dedicated inputs in the registered mode. in complex mode pin 1 and pin 13 become dedicated inputs and use the feedback paths of pin 22 and pin 15 respectively. because of this feedback path usage, pin 22 and pin 15 do not have the feedback option in this mode. in simple mode all feedback paths of the output pins are routed via the adjacent pins. in doing so, the two inner most pins ( pins 18 and 19) will not have the feedback option as these pins are always configured as dedicated combinatorial output. registered complex simple auto mode select abel p20v8r p20v8c p20v8as p20v8 cupl g20v8ms g20v8ma g20v8as g20v8 log/ic GAL20V8_r GAL20V8_c7 GAL20V8_c8 GAL20V8 orcad-pld "registered" 1 "complex" 1 "simple" 1 GAL20V8a pldesigner p20v8r 2 p20v8c 2 p20v8c 2 p20v8a tango-pld g20v8r g20v8c g20v8as 3 g20v8 1) used with configuration keyword. 2) prior to version 2.0 support. 3) supported on version 1.20 or later. pal architectures GAL20V8 emulated by GAL20V8 global olmc mode 20r8 registered 20r6 registered 20r4 registered 20rp8 registered 20rp6 registered 20rp4 registered 20l8 complex 20h8 complex 20p8 complex 14l8 simple 16l6 simple 18l4 simple 20l2 simple 14h8 simple 16h6 simple 18h4 simple 20h2 simple 14p8 simple 16p6 simple 18p4 simple 20p2 simple output logic macrocell (olmc) compiler support for olmc
4 specifications GAL20V8 in the registered mode, macrocells are configured as dedicated registered outputs or as i/o functions. architecture configurations available in this mode are similar to the common 20r8 and 20rp4 devices with various permutations of polarity, i/o and register placement. all registered macrocells share common clock and output enable control pins. any macrocell can be configured as registered or i/ o. up to eight registers or up to eight i/os are possible in this mode. dedicated input or output functions can be implemented as sub- sets of the i/o function. registered outputs have eight product terms per output. i/os have seven product terms per output. the jedec fuse numbers, including the user electronic signature (ues) fuses and the product term disable (ptd) fuses, are shown on the logic diagram on the following page. registered configuration for registered mode - syn=0. - ac0=1. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=0 defines this output configuration. - pin 1 controls common clk for the registered outputs. - pin 13 controls common oe for the registered outputs. - pin 1 & pin 13 are permanently configured as clk & oe for registered output configuration. combinatorial configuration for registered mode - syn=0. - ac0=1. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=1 defines this output configuration. - pin 1 & pin 13 are permanently configured as clk & oe for registered output configuration.. note: the development software configures all of the architecture control bits and checks for proper pin usage automatically. dq q clk oe xor xor registered mode
specifications GAL20V8 5 dip (plcc) package pinouts oe 0000 ptd 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 olmc olmc xor-2567 ac1-2639 olmc xor-2566 ac1-2638 olmc xor-2565 ac1-2637 olmc xor-2564 ac1-2636 xor-2563 ac1-2635 olmc xor-2562 ac1-2634 olmc olmc xor-2561 ac1-2633 xor-2560 ac1-2632 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) syn-2704 ac0-2705 2703 28 24 36 32 20 16 12 8 4 0 registered mode logic diagram
6 specifications GAL20V8 in the complex mode, macrocells are configured as output only or i/o functions. architecture configurations available in this mode are similar to the common 20l8 and 20p8 devices with programmable polarity in each macrocell. up to six i/os are possible in this mode. dedicated inputs or outputs can be implemented as subsets of the i/o function. the two outer most macrocells (pins 15 & 22) do not have input capability. de- signs requiring eight i/os can be implemented in the registered mode. all macrocells have seven product terms per output. one product term is used for programmable output enable control. pins 1 and 13 are always available as data inputs into the and array. the jedec fuse numbers including the ues fuses and ptd fuses are shown on the logic diagram on the following page. note: the development software configures all of the architecture control bits and checks for proper pin usage automatically. combinatorial i/o configuration for complex mode - syn=1. - ac0=1. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=1. - pin 16 through pin 21 are configured to this function. combinatorial output configuration for complex mode - syn=1. - ac0=1. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=1. - pin 15 and pin 22 are configured to this function. xor xor complex mode
specifications GAL20V8 7 dip (plcc) package pinouts 0000 ptd 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 syn-2704 ac0-2705 olmc olmc olmc olmc olmc olmc olmc olmc 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 2703 xor-2567 ac1-2639 xor-2566 ac1-2638 xor-2565 ac1-2637 xor-2564 ac1-2636 xor-2563 ac1-2635 xor-2562 ac1-2634 xor-2561 ac1-2633 xor-2560 ac1-2632 28 24 36 32 20 16 12 8 4 0 complex mode logic diagram
8 specifications GAL20V8 combinatorial output with feedback configuration for simple mode - syn=1. - ac0=0. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=0 defines this configuration. - all olmc except pins 18 & 19 can be configured to this function. combinatorial output configuration for simple mode - syn=1. - ac0=0. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=0 defines this configuration. - pins 18 & 19 are permanently configured to this function. dedicated input configuration for simple mode - syn=1. - ac0=0. - xor=0 defines active low output. - xor=1 defines active high output. - ac1=1 defines this configuration. - all olmc except pins 18 & 19 can be configured to this function. note: the development software configures all of the architecture control bits and checks for proper pin usage automatically. in the simple mode, pins are configured as dedicated inputs or as dedicated, always active, combinatorial outputs. architecture configurations available in this mode are similar to the common 14l8 and 16p6 devices with many permutations of ge- neric output polarity or input choices. all outputs in the simple mode have a maximum of eight product terms that can control the logic. in addition, each output has pro- grammable polarity. pins 1 and 13 are always available as data inputs into the and array. the ?enter?two macrocells (pins 18 and 19) cannot be used in the input configuration. the jedec fuse numbers including the ues fuses and ptd fuses are shown on the logic diagram on the following page. vcc xor vcc xor simple mode
specifications GAL20V8 9 dip (plcc) package pinouts 0000 ptd 2640 0280 0320 0600 0640 0920 0960 1240 1280 1560 1600 1880 1920 2200 2240 2520 olmc olmc olmc olmc olmc olmc olmc xor-2560 ac1-2632 olmc xor-2561 ac1-2633 xor-2562 ac1-2634 xor-2563 ac1-2635 xor-2564 ac1-2636 xor-2565 ac1-2637 xor-2566 ac1-2638 xor-2567 ac1-2639 23(27) 22(26) 21(25) 20(24) 19(23) 18(21) 17(20) 16(19) 15(18) 14(17) 13(16) syn-2704 ac0-2705 2703 11(13) 10(12) 9(11) 8(10) 7(9) 6(7) 5(6) 4(5) 3(4) 2(3) 1(2) 28 24 36 32 20 16 12 8 4 0 simple mode logic diagram
10 specifications GAL20V8 specifications GAL20V8c v il input low voltage vss 0.5 0.8 v v ih input high voltage 2.0 vcc+1 v i il 1 input or i/o low leakage current 0v v in v il (max.) 100 a i ih input or i/o high leakage current 3.5 v v in v cc 10 a v ol output low voltage i ol = max. v in = v il or v ih 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 v i ol low level output current 16 ma i oh high level output current 3.2 ma i os 2 output short circuit current v cc = 5v v out = 0.5v t a = 25 c 30 150 ma recommended operating conditions commercial devices: ambient temperature (t a ) ............................... 0 to 75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v industrial devices: ambient temperature (t a ) ........................... 40 to 85 c supply voltage (v cc ) with respect to ground ..................... +4.50 to +5.50v symbol parameter condition min. typ. 3 max. units commercial i cc operating power v il = 0.5v v ih = 3.0v l -5/-7/-10 75 115 ma supply current f toggle = 15mhz outputs open industrial i cc operating power v il = 0.5v v ih = 3.0v l-10 75 130 ma supply current f toggle = 15mhz outputs open 1) the leakage current is due to the internal pull-up resistor on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 5v and t a = 25 c absolute maximum ratings (1) supply voltage v cc ...................................... 0.5 to +7v input voltage applied .......................... 2.5 to v cc +1.0v off-state output voltage applied ......... 2.5 to v cc +1.0v storage temperature ................................ 65 to 150 c ambient temperature with power applied ........................................ 55 to 125 c 1.stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications). dc electrical characteristics over recommended operating conditions (unless otherwise specified)
specifications GAL20V8 11 specifications GAL20V8c -7 min. max. -10 min. max. t pd a input or i/o to 8 outputs switching 1 5 3 7.5 3 10 ns comb. output 1 output switching 7 ns t co a clock to output delay 1 4 2 5 2 7 ns t cf 2 clock to feedback delay 3 3 6ns t su setup time, input or feedback before clock 3 5 7.5 ns t h hold time, input or feedback after clock 0 0 0 ns a maximum clock frequency with 142.8 100 66.7 mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 166 125 71.4 mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 166 125 83.3 mhz no feedback t wh clock pulse duration, high 3 4 6 ns t wl clock pulse duration, low 3 4 6 ns t en b input or i/o to output enabled 1 6 3 9 3 10 ns b oe to output enabled 1 6 2 6 2 10 ns t dis c input or i/o to output disabled 1 5 2 9 2 10 ns c oe to output disabled 1 5 1.5 6 1.5 10 ns units parameter test cond 1 . description com/ind com com -5 min. max. 1) refer to switching test conditions section. 2) calculated from f max with internal feedback. refer to fmax descriptions section. 3) refer to fmax descriptions section. characterized initially and after any design or process changes that may affect these parameters. symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested ac switching characteristics over recommended operating conditions capacitance (t a = 25 c, f = 1.0 mhz)
12 specifications GAL20V8 specifications GAL20V8b industrial i cc operating power v il = 0.5v v ih = 3.0v l -10/-15/-25 75 130 ma supply current f toggle = 15mhz outputs open q -20/-25 45 65 ma commercial i cc operating power v il = 0.5v v ih = 3.0v l -7/-10 75 115 ma supply current f toggle = 15mhz outputs open l -15/-25 75 90 ma q -15/-25 45 55 ma recommended operating conditions commercial devices: ambient temperature (t a ) ............................... 0 to 75 c supply voltage (v cc ) with respect to ground ..................... +4.75 to +5.25v industrial devices: ambient temperature (t a ) ........................... 40 to 85 c supply voltage (v cc ) with respect to ground ..................... +4.50 to +5.50v dc electrical characteristics over recommended operating conditions (unless otherwise specified) symbol parameter condition min. typ. 3 max. units v il input low voltage vss 0.5 0.8 v v ih input high voltage 2.0 vcc+1 v i il 1 input or i/o low leakage current 0v v in v il (max.) 100 a i ih input or i/o high leakage current 3.5 v v in v cc 10 a v ol output low voltage i ol = max. v in = v il or v ih 0.5 v v oh output high voltage i oh = max. v in = v il or v ih 2.4 v i ol low level output current 24 ma i oh high level output current 3.2 ma i os 2 output short circuit current v cc = 5v v out = 0.5v t a = 25 c 30 150 ma 1) the leakage current is due to the internal pull-up resistor on all pins. see input buffer section for more information. 2) one output at a time for a maximum duration of one second. vout = 0.5v was selected to avoid test problems caused by tester ground degradation. characterized but not 100% tested. 3) typical values are at vcc = 5v and t a = 25 c absolute maximum ratings (1) supply voltage v cc ...................................... 0.5 to +7v input voltage applied .......................... 2.5 to v cc +1.0v off-state output voltage applied ......... 2.5 to v cc +1.0v storage temperature ................................ 65 to 150 c ambient temperature with power applied ........................................ 55 to 125 c 1.stresses above those listed under the absolute maximum ratings may cause permanent damage to the device. these are stress only ratings and functional operation of the device at these or at any other conditions above those indicated in the operational sections of this specification is not implied (while programming, follow the programming specifications).
specifications GAL20V8 13 specifications GAL20V8b t pd a input or i/o to 8 outputs switching 3 7.5 3 10 3 15 3 20 3 25 ns comb. output 1 output switching 7 ns t co a clock to output delay 2 5 2 7 2 10 2 11 2 12 ns t cf 2 clock to feedback delay 3 6 8 9 10 ns t su setup time, input or fdbk before clk 7 10 12 13 15 ns t h hold time, input or fdbk after clk 0 0 0 0 0 ns a maximum clock frequency with 83.3 58.8 45.5 41.6 37 mhz external feedback, 1/(tsu + tco) f max 3 a maximum clock frequency with 100 62.5 50 45.4 40 mhz internal feedback, 1/(tsu + tcf) a maximum clock frequency with 100 62.5 62.5 50 41.7 mhz no feedback t wh clock pulse duration, high 5 8 8 10 12 ns t wl clock pulse duration, low 5 8 8 10 12 ns t en b input or i/o to output enabled 3 9 3 10 15 18 25 ns b oe to output enabled 2 6 2 10 15 18 20 ns t dis c input or i/o to output disabled 2 9 2 10 15 18 25 ns c oe to output disabled 1.5 6 1.5 10 15 18 20 ns units 1) refer to switching test conditions section. 2) calculated from f max with internal feedback. refer to fmax descriptions section. 3) refer to fmax descriptions section. -25 min. max. -20 min. max. -15 min. max. -10 min. max. param. description test cond 1 . -7 min. max. symbol parameter maximum* units test conditions c i input capacitance 8 pf v cc = 5.0v, v i = 2.0v c i/o i/o capacitance 8 pf v cc = 5.0v, v i/o = 2.0v *characterized but not 100% tested. com com / ind com / ind ind com / ind ac switching characteristics over recommended operating conditions capacitance (ta = 25 c, f = 1.0 mhz)
14 specifications GAL20V8 registered output combinatorial output oe to output enable/disable input or i/o to output enable/disable f max with feedback clock width combinational output valid input input or i/o feedback t pd clk ( w/o fb ) 1/ f max t wl t wh input or i/o feedback registered output clk valid input (external fdbk) t su t co t h 1/ f max oe registered output t en t dis clk registered feedback t cf t su 1/ f max (internal fdbk) combinational output input or i/o feedback t en t dis switching waveforms
specifications GAL20V8 15 f max with internal feedback 1/( t su+ t cf) note: t cf is a calculated value, derived by subtracting t su from the period of fmax w/internal feedback ( t cf = 1/ f max - t su). the value of t cf is used primarily when calculating the delay from clocking a register to a combinatorial output (through registered feedback), as shown above. for example, the timing from clock to a combinatorial output is equal to t cf + t pd. f max with no feedback note: f max with no feedback may be less than 1/( t wh + t wl). this is to allow for a clock duty cycle of other than 50%. GAL20V8c output load conditions (see figure) test condition r 1 r 2 c l a 200 ? 200 ? 50pf b active high 200 ? 50pf active low 200 ? 200 ? 50pf c active high 200 ? 5pf active low 200 ? 200 ? 5pf test point c * l from output (o/q) under test +5v *c l includes test fixture and probe capacitance r 2 r 1 GAL20V8b output load conditions (see figure) test condition r 1 r 2 c l a 200 ? 390 ? 50pf b active high 390 ? 50pf active low 200 ? 390 ? 50pf c active high 390 ? 5pf active low 200 ? 390 ? 5pf clk register logic array t cf t pd f max with external feedback 1/( t su+ t co) note: f max with external feedback is calculated from measured t su and t co. register logic array t co t su clk input pulse levels gnd to 3.0v input rise and GAL20V8b 2 3ns 10% 90% fall times GAL20V8c 1.5ns 10% 90% input timing reference levels 1.5v output timing reference levels 1.5v output load see figure 3-state levels are measured 0.5v from steady-state active level. register logic array clk t su + t h f max descriptions switching test conditions
16 specifications GAL20V8 1.0 2.0 3.0 4.0 5.0 -60 0 -20 -40 0 input voltage (volts) input current (ua) electronic signature an electronic signature is provided in every GAL20V8 device. it contains 64 bits of reprogrammable memory that can contain user defined data. some uses include user id codes, revision numbers, or inventory control. the signature data is always available to the user independent of the state of the security cell. note: the electronic signature is included in checksum calcula- tions. changing the electronic signature will alter the checksum. security cell a security cell is provided in the GAL20V8 devices to prevent un- authorized copying of the array patterns. once programmed, this cell prevents further read access to the functional bits in the device. this cell can only be erased by re-programming the device, so the original configuration can never be examined once this cell is pro- grammed. the electronic signature is always available to the user, regardless of the state of this control cell. latch-up protection GAL20V8 devices are designed with an on-board charge pump to negatively bias the substrate. the negative bias minimizes the potential of latch-up caused by negative input undershoots. ad- ditionally, outputs are designed with n-channel pull-ups instead of the traditional p-channel pull-ups in order to eliminate latch-up due to output overshoots. device programming gal devices are programmed using a lattice semiconductor- approved logic programmer, available from a number of manu- facturers. complete programming of the device takes only a few seconds. erasing of the device is transparent to the user, and is done automatically as part of the programming cycle. typical input pull-up characteristic output register preload when testing state machine designs, all possible states and state transitions must be verified in the design, not just those required in the normal machine operations. this is because, in system operation, certain events occur that may throw the logic into an illegal state (power-up, line voltage glitches, brown-outs, etc.). to test a design for proper treatment of these conditions, a way must be provided to break the feedback paths, and force any desired (i.e., illegal) state into the registers. then the machine can be sequenced and the outputs tested for correct next state conditions. GAL20V8 devices include circuitry that allows each registered output to be synchronously set either high or low. thus, any present state condition can be forced for test sequencing. if necessary, approved gal programmers capable of executing text vectors perform output register preload automatically. input buffers GAL20V8 devices are designed with ttl level compatible input buffers. these buffers have a characteristically high impedance, and present a much lighter load to the driving logic than bipolar ttl devices. the GAL20V8 input and i/o pins have built-in active pull-ups. as a result, unused inputs and i/o's will float to a ttl "high" (logical "1"). lattice semiconductor recommends that all unused inputs and tri-stated i/o pins be connected to another active input, v cc , or ground. doing this will tend to improve noise immunity and re- duce i cc for the device.
specifications GAL20V8 17 typ. vref = 3.2v typical output typ. vref = 3.2v typical input vcc pin vcc vref active pull-up circuit esd protection circuit esd protection circuit vcc pin vcc pin vref tri-state control active pull-up circuit feedback (to input buffer) pin feedback data output circuitry within the GAL20V8 provides a reset signal to all registers during power-up. all internal registers will have their q outputs set low after a specified time ( t pr, 1 s max). as a result, the state on the registered output pins (if they are enabled) will always be high on power-up, regardless of the programmed polarity of the output pins. this feature can greatly simplify state machine design by pro- viding a known state on power-up. because of the asynchronous nature of system power-up, some conditions must be met to provide vcc clk internal register q - output feedback/external output register vcc (min.) t pr internal register reset to logic "0" device pin reset to logic "1" t wl t su a valid power-up reset of the device. first, the v cc rise must be monotonic. second, the clock input must be at static ttl level as shown in the diagram during power up. the registers will reset within a maximum of t pr time. as in normal system operation, avoid clocking the device until all input and feedback path setup times have been met. the clock must also meet the minimum pulse width requirements. power-up reset input/output equivalent schematics
18 specifications GAL20V8 delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -1 -0.75 -0.5 -0.25 0 12345678 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -1 -0.75 -0.5 -0.25 0 12345678 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -2 0 2 4 6 8 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -2 0 2 4 6 8 0 50 100 150 200 250 300 rise fall normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h GAL20V8c: typical ac and dc characteristic diagrams
specifications GAL20V8 19 vol vs iol iol (ma) vol (v) 0 0.5 1 1.5 2 0.00 20.00 40.00 60.00 80.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 voh vs ioh ioh(ma) voh (v) 3.25 3.5 3.75 4 4.25 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.80 0.90 1.00 1.10 1.20 1.30 1.40 1.50 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 2 4 6 8 10 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 input clamp (vik) vik (v) iik (ma) 0 5 10 15 20 25 30 35 40 45 -2.00 -1.50 -1.00 -0.50 0.00 GAL20V8c: typical ac and dc characteristic diagrams
20 specifications GAL20V8 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -2 -1.5 -1 -0.5 0 12345678 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -2 -1.5 -1 -0.5 0 12345678 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall GAL20V8b-7/-10: typical ac and dc characteristic diagrams
specifications GAL20V8 21 vol vs iol iol (ma) vol (v) 0 0.25 0.5 0.75 1 0.00 20.00 40.00 60.00 80.00 100.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 voh vs ioh ioh(ma) voh (v) 3.5 3.75 4 4.25 4.5 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.80 0.90 1.00 1.10 1.20 1.30 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 2 4 6 8 10 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 input clamp (vik) vik (v) iik (ma) 0 10 20 30 40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00 GAL20V8b-7/-10: typical ac and dc characteristic diagrams
22 specifications GAL20V8 normalized tpd vs vcc supply voltage (v) normalized tpd 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tco vs vcc supply voltage (v) normalized tco 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 rise fall normalized tsu vs vcc supply voltage (v) normalized tsu 0.8 0.9 1 1.1 1.2 4.50 4.75 5.00 5.25 5.50 pt h->l pt l->h normalized tpd vs temp temperature (deg. c) normalized tpd 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 pt h->l pt l->h normalized tco vs temp temperature (deg. c) normalized tco 0.7 0.8 0.9 1 1.1 1.2 1.3 -55 -25 0 25 50 75 100 125 rise fall normalized tsu vs temp temperature (deg. c) normalized tsu 0.7 0.8 0.9 1 1.1 1.2 1.3 1.4 -55 -25 0 25 50 75 100 125 pt h->l pt l->h delta tpd vs # of outputs switching number of outputs switching delta tpd (ns) -2 -1.5 -1 -0.5 0 12345678 rise fall delta tco vs # of outputs switching number of outputs switching delta tco (ns) -2 -1.5 -1 -0.5 0 12345678 rise fall delta tpd vs output loading output loading (pf) delta tpd (ns) -4 -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall delta tco vs output loading output loading (pf) delta tco (ns) -4 -2 0 2 4 6 8 10 0 50 100 150 200 250 300 rise fall GAL20V8b-15/-25: typical ac and dc characteristic diagrams
specifications GAL20V8 23 vol vs iol iol (ma) vol (v) 0 0.5 1 1.5 2 0.00 20.00 40.00 60.00 80.00 100.00 voh vs ioh ioh(ma) voh (v) 0 1 2 3 4 5 0.00 10.00 20.00 30.00 40.00 50.00 60.00 voh vs ioh ioh(ma) voh (v) 3.25 3.5 3.75 4 4.25 0.00 1.00 2.00 3.00 4.00 normalized icc vs vcc supply voltage (v) normalized icc 0.80 0.90 1.00 1.10 1.20 4.50 4.75 5.00 5.25 5.50 normalized icc vs temp temperature (deg. c) normalized icc 0.8 0.9 1 1.1 1.2 -55 -25 0 25 50 75 100 125 normalized icc vs freq. frequency (mhz) normalized icc 0.80 0.90 1.00 1.10 1.20 1.30 1.40 0 25 50 75 100 delta icc vs vin (1 input) vin (v) delta icc (ma) 0 2 4 6 8 10 12 0.00 0.50 1.00 1.50 2.00 2.50 3.00 3.50 4.00 input clamp (vik) vik (v) iik (ma) 0 10 20 30 40 50 60 70 80 90 100 -2.00 -1.50 -1.00 -0.50 0.00 GAL20V8b-15/-25: typical ac and dc characteristic diagrams

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